1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device provided with a bit line configuration by which a coupling capacitance between mutually adjacent bit lines can be reduced.
2. Description of the Related Art
FIG. 5 is a circuit diagram showing one part of a conventional ROM (Read Only Memory). In the figure, reference numerals 101 (i=1 to 6) denote memory cells. Note that although the memory cells 101i are aligned in two lines and three columns in this figure, a plurality of memory cells 101i are aligned in a matrix form in the longitudinal and lateral directions in accordance with the total memory capacity of the memory device itself in reality. Reference numerals 102i (i=1 to 6) denote transistors each configuring the corresponding memory cell, numerals 103i (i=1, 2) denote word lines which are connected to the gate of each of the transistors 102i extending in the lateral direction, and numerals 104i (i=1 to 3) denote bit lines which are extending along the transistors 102i aligned in the longitudinal direction and can be connected to the drain of each of the transistors 102i. Further, numeral 105 denotes an output line for reading data stored in the target memory cell, 106 denotes a selector for selecting the bit lines 104i connected to the output line 105, 107 denotes a signal line for transmitting a control signal for controlling the selector 106, 108 denotes a voltage source, 109 denotes a signal line for transmitting a signal for controlling the precharging operation, 110 denotes a transistor, which is switched on and off in accordance with the control signal transmitted by way of the signal line 109 and provides electric current when precharging the output line 105 and the bit line 104i selected by the selector 106, and 111 denotes a sense amplifier for converting the voltage to be fed to the output line 105 to that of the logic level in accordance with the data stored in the target memory cell.
Note that the source of each of the transistors 102i is grounded, and that storing data in the ROM shown in FIG. 5 is carried out by connecting and/or disconnecting the drain of each of the transistors 102, configuring the corresponding memory cell 101i, depending on whether the data to be stored is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In the ROM shown in FIG. 5, by connecting the drain of each of the transistors 1021, 1023, 1024, 1025 and 1026 to the respectively corresponding bit lines 104i, the binary data xe2x80x9c0xe2x80x9d (low potential VL) is stored, whereas by disconnecting, or releasing the drain of the transistor 1022 from the corresponding bit line 1042, the binary data xe2x80x9c1xe2x80x9d (high potential VH) is stored. The connection of the drain of each of the transistors with the corresponding bit line can be implemented by providing a through-hole between the drain and the corresponding bit line. Thus, forming or not forming the through-hole to each of the memory cells can be determined depending on what kind of data or program is to be stored in the ROM.
The operation of the conventional memory device is now explained below.
When reading a data, first a signal of xe2x80x9cHxe2x80x9d level is input to the signal line 109 to set ON the transistor 110, so as to precharge the output line 105 with a voltage in the region greater than the low potential VL but less than the high potential VH. Then, an appropriate signal is input to the signal line 107 thereby to connect the bit line 104i related to a read target memory cell (here, the target memory cells are considered to be of limited numbers just for convenience) with the output line 105 by way of the selector 106, so as to precharge also the bit line 104i with a voltage in the region greater than the low potential VL but less than the high potential VH, in addition to the output line 105i. After the selected bit line 104i is precharged, the voltage of the corresponding word line 103i related to the read target memory cell is set to the xe2x80x9cHxe2x80x9d level, and the transistor 102i whose gate is connected to the thus selected word line 103 is set to ON. Concerning the read target memory cell, in the case where the drain of the ON-set transistor 102i is connected to the corresponding bit line 104i (namely the case of either one of the transistors 1021, 1023, 1024, 1025 and 1026), the precharged potential flows into the ground to thereby lower the potential of the corresponding bit line 104i. Further, in the case where the drain of the ON-set transistor 102, is not connected to the corresponding bit line 104i (namely the case of the transistors 1022), the potential of the corresponding bit line 104i is not changed, and these changes of the potential are detected by the sense amplifier 111, and the voltage of the logic level corresponding to the data is output, depending on whether the binary data stored in each of the memory cells is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
FIG. 6 is a plain view showing the layout regarding one part of the configuration of a conventional ROM. The layout shown in FIG. 6 corresponds to the portion enclosed by the dotted lines shown in FIG. 5. Further, FIG. 7 is a schematic sectional view regarding the portion observed from the line cut along Axe2x80x94A of FIG. 6, whereas FIG. 8 is a schematic sectional view regarding the portion observed from the line cut along Bxe2x80x94B of FIG. 6. In these figures, reference numerals 1121 and 1122 denote gate sections made of Polysilicon (hereinafter referred to just as xe2x80x9cpolyxe2x80x9d), each of which is common to the set of transistors 1021, 1022 and 1023, and to the set of 1024, 1025 and 1026, which are connected respectively to the word lines 1031 and 1032. Numeral 113 denotes a contact for connecting a first aluminum (1AL) and the poly or a substrate, 114 denotes a first through-hole for connecting the first aluminum (1AL) and a second aluminum (2AL), and 115 denotes a second through-hole for connecting the second aluminum (2AL) and a third aluminum (3AL). It should be noted that in the plain view of the layout shown in FIG. 6, an overlap of the contact 113, the first through-hole 114 and the second through-hole 115 is represented by the overlap of symbols indicating each of these members. For example, by the symbol denoted by a reference character X, it can be deduced that the contact 113 denoted by a longitudinal line, the first through-hole 114 denoted by a lateral line and the second through-hole 115 denoted by a rightwardly ascending slant line are aligned in the vertical direction. Further, numeral 116 denotes a drain, and 117 denotes a source, wherein one source is shared by every two word lines (for example, the word line 1031 and the word line 1032) concerning the transistors configuring the memory cells connected to these two corresponding word lines. Further, numeral 118 denotes a grounding line, and by connecting the source 117 to this ground lead 118, the source 117 can be grounded. Further, in FIG. 6, the portion enclosed by the dotted lines is a diffusion region, showing the area in which each of the transistors is formed.
Since the drain of the transistor 1022 configuring a memory cell is not formed with the second through-hole as indicated by the symbol of the corresponding portion, the drain of the transistor 1022 is not connected to the bit line 1042, but is made an open output. Further, the drain of each of the transistors 1021, 1023, 1024, 1025 and 1026 is, as shown by the symbol of the corresponding portion, formed with the second through-hole, so that the drain of each transistor is connected to the third aluminum (3AL), namely to the bit line 1041.
Since the conventional semiconductor memory device is configured as mentioned above, all the bit lines are configured by the metal lines in the same layer, and in accordance with a progress of the process integration, the space between mutually adjacent bit lines is made narrower, so that such a problem arises that the specific gravity of the coupling capacitance occupied within the whole bit-line capacitance is made large, so that an erroneous operation occurs due to this coupling capacitance.
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a semiconductor memory device which is capable of reducing the coupling capacitance between mutually adjacent bit lines and thereby reducing the occurrence of erroneous operations.
In order to achieve the above object, a semiconductor memory device according to the first aspect of the present invention is configured in such a manner that it comprises a plurality of memory cells aligned in a matrix form, and a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, wherein each of the bit lines is provided with a line section of the upper layer and that of the lower layer, and that the mutually adjacent portions of the respectively adjacent two bit lines are provided in the different layers from each other.
A semiconductor memory device according to another aspect of the present invention is configured such that it comprises a plurality of memory cells aligned in a matrix form, and a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, wherein a line section for grounding (or just line grounding section) is disposed between the mutually adjacent bit lines.
A semiconductor memory device according to a further aspect of the present invention is constructed such that the bit lines and the line sections for grounding are provided in the same layers.
A semiconductor memory device according a slightly different aspect of the above is constructed such that the bit lines and the line sections for grounding are provided in the different layers.
A semiconductor memory device according further aspect of the present invention is configured such that it comprises a plurality of memory cells aligned in a matrix form, and a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, wherein the drain of all or some of the transistors configuring the memory cells in the area where no customer""s program is stored (non-programmed area) are connected to the bit lines.
A semiconductor memory device according a further aspect of the present invention is constructed such that in the area where no customer""s program is stored, the drain of of each of the transistors configuring the less number of memory cells than those connectable to the bit lines is connected to the corresponding bit line for obtaining the required reading speed margin per each bit line.
A semiconductor memory device according a still further aspect of the present invention is constructed such that it comprises a plurality of memory cells aligned in a matrix form, a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, an output means which is connected to either one of the bit lines and outputting a signal of the voltage level corresponding to the data stored in the selected memory cell, an inverting means which is connected to the data output line and inverting an input signal, a line section which is connected to the data output line in parallel to the inverting means, and a selection means for selecting either the inverting means or the line section to which the output means is to be connected.
A semiconductor memory device according a still further aspect of the present invention is constructed such that it comprises a plurality of memory cells aligned in a matrix form, and a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, wherein selectively one or plural bit lines are formed in the layer which is different from that where other bit lines are formed.